1. Field of the Invention
The present invention relates generally to electrically programmable, electrically erasable, read only memory (EEPROM) devices and, in particular, to a flash EEPROM suitable for low voltage operation.
2. Background Art
Electrically programmable read only memories are non-volatile memories which utilize a floating gate structure. EEPROM's, or electrically erasable, electrically programmable memories, include memories wherein the cells may be individually programmed and erased. However, this type of EEPROM, commonly referred to as a standard EEPROM, requires a wide range of voltages for programming, reading and erasing and the cells are relatively large.
Flash EEPROMs have been developed which have a smaller cell size then standard EEPROM. Flash EEPROMs have cells that cannot be individually erased, but are erased in bulk.
Referring now to the drawings, FIG. 1A depicts a conventional flash memory cell, commonly referred to as the Intel ETOX cell or simply the ETOX cell. The cell includes a graded N type source region 20 diffused into a P type substrate 22. An N type drain region 24 is also diffused into the substrate 22 so as to define a channel region 22a between the source and drain regions.
A polysilicon floating gate 26 is disposed above the channel 22a and is separated from the channel by a thin (about 100 .ANG.) gate oxide 28. A polysilicon control gate 30 is disposed above the floating gate 26 and is separated from the floating gate by an interpoly dielectric layer 32.
As shown in FIG. 1A, the ETOX flash cell is programmed by applying a programming voltage Vpp (typically +6 to +9 volts) to the drain region 24 and a higher voltage Vgg (typically +10 to +13 volts) to the control gate. The source region is grounded (Vss). Voltage Vpp is usually supplied from an external source and voltage Vgg is usually provided by way of a charge pump type circuit.
The positive charge on the control gate 30 results in avalanche or hot electron injection near the drain 24 and into the polysilicon floating gate 26. As will be explained, a programmed cell has characteristics which differ from an unprogrammed cell.
The conventional ETOX cell is read in the manner shown in FIG. 1B. The source region 20 is grounded (Vss) and an intermediate voltage Vr (typically +1 to +2 volts) is applied to the drain region 24. Voltage Vcc, the primary supply voltage, is applied to the control gate 30. Voltage Vcc is typically +5 volts. In the case where the cell had been previously programmed, the negative charge present on the floating gate will tend to prevent the positive voltage on the control gate 30 from inverting the channel.
Thus, the negative charge effectively increases the threshold voltage of the cell so that the cell will not be rendered conductive by the voltage Vcc applied to the control gate 30. Accordingly, no current flow will take place through the cell.
In the event the cell of FIG. 1B was not previously programmed, the threshold voltage of the cell will be sufficiently low such that the cell will be rendered conductive by voltage Vcc. This will result in current flow through the cell which will be detected by the sense amplifier.
The ETOX cell is erased in the manner depicted in FIG. 1C. The drain region 24 is left open (floating) and control gate 30 is grounded (Vss). Positive voltage Vpp is applied to the source region 20 which results in electrons being drawn off floating gate 26 through the thin gate oxide 28 to the graded source region 20. The mechanism for such removal of electrons is known as Fowler-Nordheim tunneling.
The voltage Vcc applied to the control gate 30 (FIG. 1B) in read operations is typically the primary supply voltage of the memory system. There has been a tendency to reduce the magnitude of Vcc from +5 volts to lower values such as +3 volts so that battery powered operation may be achieved. However, low values of Vcc may be insufficient to adequately drive the memory cells during read operations. In that event, the magnitude of cell current produced when an unprogrammed cell is read may be so small the current cannot be reliably detected by the sense amplifier. Further, low cell current increases the time required to read the cell, a particular disadvantage in high speed memory applications.
It would be possible to increase the voltage Vcc applied to the gate during read operations utilizing a charge pump type circuit. However, the gate voltage must be switched rapidly during read operations for high speed memory applications. Charge pump circuits do not possess sufficient speed to accomplish this task.
The present invention overcomes the above-noted shortcoming of conventional flash memory cells when operated at low supply voltages. Reliable read operations are achieved for supply voltages as low as +3 volts and below. This and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.